1. Field of the Invention
The invention relates in general to integrated circuits, and more particularly, to integrated circuits that include phase lock loop circuits or delay lock loop circuits.
2. Description of the Related Art
Integrated circuits often employ phase-locked loop (PLL) or delay-locked loop (DLL) circuitry to synthesize a clock signal frequency from a reference clock signal. A programmable logic device is a type of integrated circuit that can use a PLL or DLL to generate a clock signal at a desired frequency and also to help counteract clock skew and excessive delay in clock signals propagating within the device. For convenience herein PLL and DLL circuitry is sometimes referred to generically herein as PLL/DLL circuitry. Sung et al. U.S. Pat. No. 6,252,419; Sung et al. U.S. Pat. No. 6,218,876; and Sung et al. U.S. Pat. No. 6,177,844; and Jefferson et al. U.S. Pat. No. 5,744,991 which describe the use of PLL/DLL circuits in integrated circuits, particularly in programmable logic device integrated circuits, are expressly incorporated herein by this reference.
PLL/DLL circuits typically include a loop filter. One function of a loop filter is to filter out high frequency harmonics in the loop. Another function of the loop filter is to stabilize the loop. The loop filter also affects loop response parameters such as loop bandwidth, loop time response and the damping factor of the loop.
The loop bandwidth influences PLL/DLL circuit responsiveness to changes in reference clock signal frequency. A higher loop bandwidth results in a PLL/DLL that is more rapidly responsive. A lower loop bandwidth results in a PLL/DLL that is less rapidly responsive. In some applications, it is desirable for the PLL/DLL to be highly responsive to changes in reference clock signal frequency. In other applications it is desirable for the loop filter to less responsive to changes in the reference clock signal frequency.
A higher bandwidth loop filter is more desirable where a more quickly responsive PLL/DLL is required. For example, certain memory modules typically employ a PLL/DLL circuit to control timing of memory access signals. Generally, it is desirable to employ a PLL/DLL with a higher bandwidth in such memory modules so that the PLL/DLL responds more rapidly to rapid changes in the reference clock signal. This responsiveness contributes to the achievement of high-speed access to memory.
A lower bandwidth loop filter is more desirable where a less quickly responsive PLL/DLL is required. For instance, in some systems it is not unusual to experience reference clock jitter. Such reference clock jitter can be regarded as a form of electronic noise. In some such systems it is important that a PLL/DLL phase-locked to a reference clock not be overly responsive to reference clock jitter or noise. For example, in video applications, a PLL/DLL that is too responsive to a jittery reference clock can result in a flickering distortion of an image displayed on a video screen. As another example, in certain radio frequency (RF) communications systems it is important that a PLL/DLL synthesize an output clock signal frequency that remains within a relatively narrow frequency range despite reference clock jitter or other noise sources. For instance, in an RF communications system compliant with the IS-54A standard, the lower end frequency range is 869 MHz, and the channel frequency spacing is 30 kHz. Thus, it is important that a PLL/DLL used to synthesize a clock signal within given relatively narrow channel have the ability to remain locked within a desired channel despite clock jitter.
In view of the wide range of PLL/DLL circuitry applications, there has been an increasing need for more versatile PLL/DLL circuitry. One problem with providing such PLL/DLL circuitry is that while a high bandwidth loop filter typically is small enough to fit on the same integrated circuit as the PLL/DLL circuitry, a low bandwidth loop filter often is too large to fit on one integrated circuit with other PLL/DLL components. Another problem is that feedback circuitry typically employed in PLL/DLLs used in some general purpose high bandwidth applications typically is different from feedback circuitry ordinarily employed in other lower bandwidth applications such as RF communications, for example. Despite these problems, the present invention meets the need for an integrated circuit with PLL/DLL circuitry that is adaptable to high bandwidth and to low bandwidth applications.
The present invention provides an integrated circuit including phase lock loop or delay lock loop (PLL/DLL) circuitry. The PLL/DLL circuitry has feedforward circuitry which includes a phase/frequency detector (PFD) circuit including a reference clock input connected to a clock input terminal and a PFD feedback input and a PFD output. The PLL/DLL feedforward circuit also includes a charge pump (CP) circuit, a loop filter (LF) and a loop controlled signal source (LCSS). The PLL/DLL circuitry further includes a feedback circuit connected between a LCSS output and the PFD feedback input. The feedback circuit includes an external feedback input terminal The feedback circuitry also includes first frequency selection circuitry to produce a first programmable feedback signal and second frequency selection circuitry to produce a second feedback signal. The feedback circuitry includes multiplex circuitry connected with the LCSS output, the external feedback input terminal and the first and second frequency selection circuitry, to cause either the first programmable feedback signal or the second programmable feedback signal to be coupled to the PFD feedback input. Moreover, the PLL/DLL circuitry includes at least one external feedforward output terminal which is connectable to an external PLL/DLL feedforward circuit component.
The external feedforward output terminal can be used to connect the PLL/DLL circuitry as part of a hybrid PLL/DLL circuit that includes external feedforward components, such as an external loop filter, for example. The multiplex circuitry can be used to switchably couple the first or second feedback signals to the PFD input depending upon the application of the PLL/DLL circuitry. For example, on the one hand, if the PLL/DLL circuitry is connected with an physically large external low bandwidth loop filter, then the multiplex circuitry can be switched to couple to the PFD input the one of the first and second feedback signals most suitable for low bandwidth applications. On the other hand, if the PLL/DLL circuitry is connected with a higher bandwidth on-chip loop filter, then the multiplex circuitry can be switched to couple to the PFD input the one of the first and second feedback signals most suitable for high bandwidth applications.
Therefore, the present invention meets the need for an integrated circuit with PLL/DLL circuitry that is adaptable to high bandwidth and to low bandwidth applications.